Semiconductor device and manufacturing method thereof

ABSTRACT

A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 80% or more, and an n-channel MIS transistor formed on a p-type well on the substrate, having a second gate dielectric and a second gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 60% or less.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromprior Japanese Patent Application No. 2005-356951, filed Dec. 9, 2005,the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device in which ap-channel MIS transistor and an n-channel MIS transistor are formed onthe same substrate, and more particularly, it relates to a semiconductordevice with an improved gate electrode structure and a manufacturingmethod thereof.

2. Description of the Related Art

Recently, in silicon complementary metal insulator semiconductor (CMIS)devices, an attempt has been made to use, as a gate electrode, arefractory metal such as titanium, molybdenum, tungsten or tantalum, ora nitride thereof. This is what is called a metal gate technique.

In the metal gate technique, depletion layers are not generated withinthe gate electrode in principle, and there is therefore no decreasecaused in current drivability of a MIS transistor due to the depletionlayers, in contrast with the case of a silicon gate. A TaCx metal gatetechnique is described in, for example, J. K. Schaeffer et al.,“Challenges for the Integration of Metal Gate Electrodes”, 2004 IEDM,p.p. 287 to 309). However, in this document, there is no report onphysical property values other than the work function and specificresistance regarding TaCx physical properties.

Furthermore, there is a so-called dual metal gate technique in which ametal gate electrode having the same work function as that of n⁺ siliconis disposed for an n-channel MIS transistor and a metal gate electrodehaving the same work function as that of p⁺ silicon is disposed for ap-channel MIS transistor. In the dual metal gate technique, a thresholdvoltage can be controlled in the same manner as the conventional silicongate technique, and it is possible to design a transistor having a lowthreshold voltage.

However, in the dual metal gate technique, since materials of the gateelectrodes in the p-channel MIS transistor and the n-channel MIStransistor are different, film formation for these gate electrodes needsto be separately carried out, so that this technique has a large problemin that the gate electrodes have to be processed independently for thep-channel MIS transistor and the n-channel MIS transistor, in additionto problems such as increased film formation process steps andcomplication. This dual metal gate technique is most desirable in termsof transistor performance, but the above-mentioned problem of thecomplication of its manufacturing method has to be solved to achievethis technique.

As has been described, it is essential to replace the conventionalsilicon gate and introduce the metal gate technique in order to improvethe current drivability of the transistor and realize a silicon CMISdevice with a high processing speed. The dual metal gate technique isessential for enhanced performance because it can set a low thresholdvoltage of the transistor, but the complication of its manufacturingmethod has been the major obstacle to practical application.

It has therefore been desired to achieve a semiconductor device and amanufacturing method thereof capable of realizing a dual metal gatestructure whose manufacturing method is easy and contributing to acharacteristic improvement of the CMIS devices and the like.

BRIEF SUMMARY OF THE INVENTION

According to a first aspect of the invention, there is provided asemiconductor device, which includes:

a substrate;

a p-channel MIS transistor formed on an n-type well on the substrate,having a first gate dielectric film formed on the n-type well, and afirst gate electrode formed on the first gate dielectric film, the firstgate electrode formed of a Ta—C alloy in which a crystal orientationratio of a TaC (111) face in a film thickness direction of the firstlower layer gate electrode [TaC (111) face/{TaC (111) face+TaC (200)face}] is 80% or more; and

an n-channel MIS transistor formed on a p-type well on the substrate,having a second gate dielectric film formed on the p-type well, and asecond gate electrode formed on the second gate dielectric film, thesecond gate electrode formed of a Ta—C alloy in which a crystalorientation ratio of a TaC (111) face in a film thickness direction ofthe second lower layer gate electrode [TaC (111) face/{TaC (111)face+TaC (200) face}] is 60% or less.

According to a second aspect of the invention, there is provided amethod of manufacturing a semiconductor device, which includes:

preparing a substrate having an n-type semiconductor area and a p-typesemiconductor area insulated from each other;

forming gate dielectric films on the n-type semiconductor area and thep-type semiconductor area, respectively;

alternately supplying tantalum (Ta) and carbon (C) on the gatedielectric film on the n-type semiconductor area to form a first Ta—Calloy film in which a crystal orientation ratio of a TaC (111) face in afilm thickness direction [TaC (111) face/{TaC (111) face+TaC (200)face}] is 80% or more;

simultaneously supplying tantalum (Ta) and carbon (C) onto the gatedielectric film on the p-type semiconductor area to form a second Ta—Calloy film in which a crystal orientation ratio of a TaC (111) face in afilm thickness direction [TaC (111) face/{TaC (111) face+TaC (200)face}] is 60% or less; and

processing the first TaC alloy film on the n-type semiconductor area andthe second TaC alloy film on the p-type semiconductor area into gateelectrode patterns.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 is an elemental structure sectional view showing a schematicconfiguration of a semiconductor device according to a first embodiment;

FIG. 2 is a characteristic chart showing a orientational change of aTaCx electrode due to a difference of film formation methods;

FIG. 3 is a characteristic chart showing a relation between theorientation and work function of a TaCx electrode;

FIG. 4 is a characteristic chart showing a relation between thecomposition and crystallinity change of a TaCx electrode;

FIGS. 5A and 5B explain a change in heat resisting performance of a MISstructure in accordance with a change in composition ratio (C/Ta) ofTaCx, and are photomicrographs showing sectional TEM images of the TaCxelectrode;

FIG. 6 is a schematic diagram showing grounds for the stipulation of amixing ratio (C/Ta) between Ta and C;

FIGS. 7A to 7L are sectional views showing step by step a process ofmanufacturing the semiconductor device according to the firstembodiment;

FIGS. 8A to 8C are schematic diagrams for explaining a method of forminga TaCx electrode for pMIS;

FIGS. 9A to 9C are schematic diagrams for explaining a method of forminga TaCx electrode for nMIS;

FIGS. 10A and 10B are photomicrographs showing sectional TEM images of astructure composed of the TaCx electrode for nMIS, SiO₂ and Si at thecompletion of the device in the first embodiment;

FIG. 11 is an elemental structure sectional view showing a schematicstructure of a semiconductor device according to a second embodiment;

FIGS. 12A to 12D are sectional views showing step by step a process ofmanufacturing the semiconductor device according to the secondembodiment;

FIG. 13 is a sectional view showing a schematic structure of asemiconductor device according to a third embodiment;

FIGS. 14A to 14H are sectional views showing step by step a process ofmanufacturing the semiconductor device according to the thirdembodiment;

FIG. 15 is a photomicrograph showing a sectional TEM image of a TaCxfilm in the case of C/Ta≅2.7;

FIG. 16 is a schematic diagram for explaining the characteristics of aTaCx electrode;

FIG. 17 is a sectional view showing a schematic structure of asemiconductor device according to a fourth embodiment;

FIGS. 18A to 18I are sectional views showing step by step a process ofmanufacturing the semiconductor device according to the fourthembodiment; and

FIG. 19 is a diagram for explaining an improvement of the work functionof the semiconductor device according to the fourth embodiment.

DETAILED DESCRIPTION OF THE INVENTION

Before describing embodiments, the outline and principle of the presentinvention will first be described.

One embodiment of the present invention concerns a semiconductor devicecomprising a CMIS device as shown in FIG. 1, and is mostly characterizedby having crystallized TaCx as gate electrodes for both a p-channel MIStransistor and an n-channel MIS transistor, wherein TaCx of thep-channel MIS transistor has a strong (111) orientation, and (200)orientation components of the n-channel MIS transistor are increased tobring the work functions of the respective gate electrodes to those ofp⁺ silicon and n⁺ silicon, thus achieving a dual metal gate by a singlematerial TaCx.

It is to be noted that, in FIG. 1, the reference numeral 11 denotes anSi substrate, 22 denotes an n-type well, 23 denotes a p-type well, 24denotes an isolation insulator, 25 denotes a p-type diffusion layer, 26denotes a p-type extension layer, 27 denotes an n-type diffusion layer,28 denotes an n-type extension layer, 31 denotes a gate dielectric film,32 denotes a p-channel side TaCx gate electrode, 33 denotes an n-channelside TaCx gate electrode, 34 denotes a gate sidewall insulator, 35denotes an interlayer insulator, 51 denotes a p-channel MIS transistor,and 52 denotes an n-channel MIS transistor.

On the other hand, a TaCx metal gate technique is described in theabove-mentioned document. The difference between this prior art and thepresent invention is that while TaCx is used for both the p-channel MIStransistor and the n-channel MIS transistor in the present invention, aTaCx electrode is only used in the n-channel MIS transistor in the priorart. The prior art has such a limitation because the work function ofthe TaCx electrode is 4.18 eV. Even if TaCx of the prior art is used inthe gate electrode of the p-channel MIS transistor, its thresholdvoltage becomes very high, and a normal operation of the CMIS isimpossible. In addition, there is no report, in the above-mentioneddocument, on physical property values other than a work function andspecific resistance regarding TaCx physical properties.

In the present embodiment, the composition ratio (C/Ta) between Ta and Cis set at 0.5 to 1.5, and TaCx is used in a crystallized state. Further,the present inventors have newly found out that the (111) orientationcan be intensified to obtain a work function of about 4.8 eV close tothat of p⁺ silicon and that the (200) orientation components can beincreased in relation to the (111) orientation to obtain a work functionclose to that of n⁺ silicon. This is applied to the dual metal gate of aCMIS transistor.

FIG. 2 shows experimental results of the examination of thecrystallinity of a TaCx thin film having a thickness of 100 nm in theabove discovery. The abscissa indicates an angle (2θ), and the ordinateindicates intensity. In addition, an offset is indicated in an ordinatedirection so that characteristics of a TaC electrode for pMIS can bedifferentiated from characteristics of a TaC electrode for nMIS. Thecomposition of TaCx films is C/Ta≅1, but it has been proved that thedifference of film formation methods enables separate formation of afilm having the strongest (111) diffraction peak and a film having thestrongest (200) diffraction peak.

The result of using an analytical sample including a TaC film, a gatedielectric film and an Si substrate has been shown above. It should beunderstood that such an experiment can also be conducted with acompleted transistor, in which case a part corresponding to a gateelectrode of the transistor is cut out by a pickup method used in, forexample, transmission electron microscopy (TEM), and the section of thegate electrode is analyzed by an electron diffraction method, such thatit is possible to check the proportion of the (111) orientation to the(200) orientation. In this case, positioning accuracy regardinganalyzing position is high because an electron beam of the TEM method isused. This makes it easy to check the orientation of the TaC film in anarea contacting the gate dielectric film which is actually associatedstrongly with threshold voltage control.

FIG. 3 is a diagram showing a change of the work function when theorientation is changed as described above. It has been found out that acrystal orientation ratio α of the (111) face indicated by Equation (1)below needs to be 80% or more because TaCx shows a work function of 4.75eV or more which is equal to that of p⁺ silicon.

α=TaC (111) face/{TaC (111) face+TaC (200) face}×100  (1)

Here, the (111) face crystal orientation ratio α is calculated fromEquation (1) after obtaining absolute values of TaC (111) peak intensityand TaC (200) peak intensity in X-ray diffraction (XRD) spectra in FIG.2. Here, peak areas may be used instead of the peak intensities.Moreover, when the (111) face crystal orientation ratio is obtained, areference is set to a direction vertical to a surface of the gateelectrode adjacent to the gate dielectric film, that is, a thicknessdirection of the gate film.

On the other hand, the present inventors have found out that the (111)crystal orientation ratio needs to be 60% or less because TaCx shows awork function of 4.4 eV or less which is equal to that of n⁺ silicon.

It is to be noted that the (111) face crystal orientation ratio is moredesirably 90% or more for the p-channel MIS transistor and 5% or lessfor the n-channel MIS transistor. Thus, it is possible to set 4.9 eV ormore for the p-channel MIS transistor and 4.2 eV or less for then-channel MIS transistor which are threshold voltages sufficiently lowfor a bulk-type CMIS device.

In addition, the (111) face crystal orientation ratio is calculated inFIG. 2 at 84% for the upper spectrum and 10% for the lower spectrum. Thework functions of the TaC electrodes at this point are 4.80 eV and 4.25eV, showing values which are sufficient to set a low threshold voltageof a bulk CMIS transistor.

FIG. 4 concerns experimental results showing an orientational change inaccordance with a change of the composition ratio (C/Ta) of TaCx. Thesame technique was used for the thin film formation in this experiment.The crystal diffraction intensity of a film weakens along with anincrease of C/Ta, and no diffraction peak is obtained at a C/Ta of 2.7.It is premised that TaCx of the present invention is crystallized. Anexperiment in which the composition is more finely changed proves thatC/Ta as a requisite for the crystallization of TaCx is 1.5 or less.

FIGS. 5A and 5B show sectional TEM photographs of a TaCx/SiO₂ structureobserved after thermally treated at 1000° C. to decide a lowerconcentration limit of C/Ta. A TaCx/SiO₂ interface does not at allappear to be reacting in the case of C/Ta≅1.0 even after the thermaltreatment at 1000° C. On the contrary, in the case of C/Ta<0.5, it hasbeen found out that an interface reaction layer having a thickness ofnearly 2 nm is produced in the TaCx/SiO₂ interface by the thermaltreatment at 1000° C. The reaction layer precludes practical applicationbecause it causes performance deterioration such as work functionmodulation and electric trap formation.

Through the above preliminary experiment, compositional characteristicsof dual metal gate TaCx of the present invention are stipulated asfollows. First, C/Ta is 1.5 or less because the film has to becrystallized to obtain the function of a dual metal in crystalorientation control in the present invention. On the other hand, C/Tahas to be 0.5 or more from the viewpoint of maintaining properties ofresisting a heat >1000° C. Thus, TaCx of the present invention isstipulated within a range of 0.5≦C/Ta≦1.5. A limitation range of theC/Ta ratio in the present invention is schematically shown in FIG. 6.

Thus, as a result of examining the physical characteristics of the TaCxthin film in detail, the present inventors have found out that if theTaCx film is crystallized in a certain C/Ta composition ratio while itsorientation is controlled, the TaCx work function can be modulated to becloser to that of n⁺ silicon or p⁺ silicon. The present invention hasbeen carried out on the basis of this new discovery, and has aconfiguration and an advantage different from those in the category ofprior arts.

The structure in the present invention has a great advantage that theprocessing of the gate electrodes can be collectively carried outbecause the gate electrodes of both the p-channel MIS transistor and then-channel MIS transistor are TaCx. Thus, the number of process steps isremarkably reduced as compared with the case where another material isused as in the conventional dual metal gate, and moreover, thedevelopment of an etching process is reduced. This drastically advancesthe practicability of the dual metal gate.

The configuration whose outline has been described above makes itpossible to provide, through an easy process, a semiconductor devicecomprising a high-performance metal gate CMIS device capable of settinga low threshold voltage and having no gate depletion.

In other words, the crystal orientation ratios of the TaC (111) faces ofthe gate electrodes of the p-channel and n-channel MIS transistors canbe optimally set to achieve work functions suitable for the respectivechannels. In this case, the gate electrodes of the respective MIStransistors are based on the same material, such that a manufacturingprocess can be simplified.

Details of the present invention will hereinafter be described throughthe embodiments.

FIRST EMBODIMENT

As shown in FIG. 1, in a semiconductor device according to a firstembodiment of the present invention, an n-type well area 22 and a p-typewell area 23 are provided on an Si substrate 11. The n-type well area 22is separated from the p-type well area 23 by an isolation insulator 24having a shallow trench isolation (STI) structure. It is to be notedthat a bulk substrate is used as the substrate in the presentembodiment, but a silicon on insulator (SOI) substrate can also be used.

The n-type well area 22 is provided with a p-channel MIS transistor 51.The p-channel MIS transistor 51 comprises a p-type diffusion layer 25, ap-type extension layer 26, a gate dielectric film 31 and a TaCx gateelectrode for pMIS 32. The gate dielectric film 31 is provided on then-type well area 22, and the TaCx gate electrode for pMIS 32 is providedon the gate dielectric film 31. It is to be noted that in the presentembodiment, sidewalls 34 made of an insulating material such as asilicon nitride film or a silicon oxide film are provided on both sidesof a stacked structure of the gate dielectric film 31 and the TaCx gateelectrode for pMIS 32.

Furthermore, the p-type extension layers 26 are provided in the n-typewell areas 22 on both sides of the stacked structure of the gatedielectric film 31 and the TaCx gate electrode for pMIS 32, and thep-type diffusion layers 25 are provided in the n-type well area 22 onopposite sides of the sidewalls 34. The p-type diffusion layer 25 isconfigured so that it is bonded to the n-type well area 22 more deeplythan the p-type extension layer 26. Moreover, the p-type diffusion layer25 and the p-type extension layer 26 serve as source/drain areas of thep-channel MIS transistor 51.

On the other hand, an n-channel MIS transistor 52 is provided in thep-type well area 23. The n-channel MIS transistor 52 comprises an n-typediffusion layer 27, an n-type extension layer 28, a gate dielectric film31 and a TaCx gate electrode for nMIS 33. The gate dielectric film 31 isprovided on the p-type well area 23, and the TaCx gate electrode fornMIS 33 is provided on the gate dielectric film 31. It is to be notedthat in the present embodiment, sidewalls 34 made of an insulatingmaterial are provided on both sides of a stacked structure of the gatedielectric film 31 and the TaCx gate electrode for nMIS 33.

Furthermore, the n-type extension layers 28 are provided in the p-typewell area 23 on both sides of the stacked structure of the gatedielectric film 31 and the TaCx gate electrode for nMIS 33, and then-type diffusion layer 27 is provided in the p-type well area 23 onopposite sides of the sidewalls 34. The n-type diffusion layer 27 isconfigured so that it is bonded to the p-type well area 23 more deeplythan the n-type extension layer 28. Moreover, the n-type diffusion layer27 and the n-type extension layer 28 serve as source/drain areas of then-channel MIS transistor 52.

Next, a method of manufacturing the semiconductor device of the presentembodiment will be described referring to FIGS. 7A to 7L.

First, as shown in FIG. 7A, the n-type well area 22 and the p-type wellarea 23 which are separated by the isolation insulator 24 are formed onthe Si substrate 11. Subsequently, the gate dielectric film 31 and theTaCx electrode for pMIS 32 are deposited over the entire surface on awafer.

The high dielectric film that can be used includes, for example, anoxide or mixed oxide of rare-earth elements such as Ti, Hf, Zr and La,silicate or aluminate of rare-earth elements such as Ti, Hf, Zr and Laor a dielectric film in which nitrogen is added to the above materials,Si₃N₄, Al₂O₃, Ta₂O₅, TiO₂, La₂O₃, CeO₂, ZrO₂, HfO₂, SrTiO₃, Pr₂O₃ or adielectric film in which nitrogen is added to the above materials. Here,SiON having a thickness of 1.5 nm is deposited by thermal oxidation andplasma nitridation by way of example. To form the high-K gate dielectricfilm, it is possible to use a metal organic chemical vapor deposition(MOCVD) method, an atomic layer deposition (ALD) method, a molecularbeam epitaxy (MBE) method, a physical vapor deposition (PVD) method orthe like.

The TaCx electrode for pMIS 32 is formed by sputtering under Aratmosphere using a TaC compound target in which the composition ratio(C/Ta) between Ta and C is adjusted to a range of 0.5 to 1.5. Thecomposition ratio (C/Ta) in the present embodiment is 1.0, and the filmthickness is 100 nm. Further, this method can be implemented when theflow of Ar ranges from 1 to 20 sccm, a voltage applied to the TaC targetis 50 to 500 W, and the degree of vacuum within the device during thesputtering ranges from 0.01 to 0.4 Pa. Thus, it is possible to form theTaC electrode 32 in which a (111) face crystal orientation ratio is 80%or more. The TaC layer formed in the above method has stress within thefilm thereof, and this stress serves as driving force for preferentialorientation on a (111) face.

Furthermore, it is advantageous that Ta layers and C layers arealternately present in a film thickness direction in order toefficiently form the TaC electrode for pMIS 32 in which the (111) facecrystal orientation ratio is 80% or more. The principle of this filmformation method is schematically shown in FIGS. 8A to 8C. TaC assumes acubic crystal structure, and its (111) face has a structure in which theTa layers and the C layers are alternately stacked. Therefore, an atomicarrangement similar to that on the (111) face is intentionally formed atthe stage of film formation, such that it is possible to moreefficiently obtain a TaC thin film oriented on the (111) face.

Such a manufacturing method can be achieved by a technique similar tothe atomic layer deposition (ALD). That is, the supply of Ta source andthe supply of C source can be alternately carried out layer by layer asshown in FIGS. 8A to 8C. That is, tantalum 32 a is deposited for oneatomic layer (FIG. 8A), and carbon 32 b is deposited thereon for oneatomic layer (FIG. 8B), and then tantalum 32 a is deposited thereon forone atomic layer (FIG. 8C). Here, it is possible to use, as the Tasource, a material with relatively high vapor pressure, such as achloride base, amide base or imide base material. As the C source, it ispossible to use, for example, acetylene, CH₄, C₂H₄, CCl₄, or CO.

Furthermore, a sputtering method can also be used to achieve themanufacturing method described above. In this case, a multi-cathodesputtering apparatus having a plurality of cathodes is used, to which aTa target and a C target are attached. Sputtering for one layer of theTa target and sputtering for one layer of the C target can bealternately carried out to form a TaC thin film for pMIS.

Here, the order of forming films on the gate dielectric film does notgreatly influence the orientation on the (111) face, regardless ofwhether the film formation is started with C or Ta. However, when thefilm formation is started with C on the gate dielectric film, C ispresent on the gate dielectric film without being bonded to Ta,resulting in a situation where carbon is more likely to move into thegate dielectric film at this film formation stage. It is known that Cwithin the gate dielectric film originates a fixed charge and causedevice characteristics to deteriorate. Therefore, in the presentembodiment, the Ta layer is first deposited.

Furthermore, if the surface of the TaCx electrode for pMIS 32 isoxidized at a significantly small thickness after this step, the processresistance of the TaCx electrode in subsequent steps is improved. Here,spike annealing at 1000° C. is carried out under 1% oxygen atmosphere toform an oxide layer having a thickness of 1 nm or less on the TaCxsurface.

Next, an SiN layer 36 is deposited all over the surface of the structurein FIG. 7A, and the top of the n-type well area 22 is only covered withthe SiN layer 36 using a conventional lithographic technique and etchingtechnique. Using this SiN layer 36 as a mask, the TaCx electrode forpMIS 32 on the p-type well area 23 is removed by an ordinary etchinggas. Thus, the structure in FIG. 7B is obtained.

Next, the TaCx electrode for nMIS 33 is deposited all over the surfaceof the structure in FIG. 7B, and the structure in FIG. 7C is obtained.In order to form the TaCx electrode for nMIS 33 in which the (111) facecrystal orientation ratio is 60% or less, it is important that a film isformed so that the Ta atomic layers and the C atomic layers are notalternately present in the film thickness direction, in contrast to theformation of the TaCx electrode for pMIS 32 previously described.Schematic diagrams for the principle of this film formation are shown inFIGS. 9A to 9C.

In order to form the TaCx electrode for nMIS 33 by a CVD method, it isimportant that the Ta source and the C source are simultaneouslysupplied. That is, tantalum atoms 33 a and carbon atoms 33 b aredeposited in parallel on the dielectric film 31 (FIG. 9A), and thecarbon atoms 33 b are deposited on the tantalum atoms 33 a and thetantalum atoms 33 a are deposited on the carbon atoms 33 b (FIG. 9B),and this is repeated in the similar manner (FIG. 9C). Thus, theformation of TaC is implemented so that Ta and C coexist in one layer,and therefore, the (111) face is not easily formed, or rather, the (200)face is easily formed. Here, the Ta source and the C source may beidentical with those used for the formation of the TaCx electrode forpMIS 32.

When the sputtering method is used, it is desirable to use simultaneoussputtering of the Ta target and the C target. In this case, Ta and C aresimultaneously sputtered, such that the (111) face is not easily formedand the (200) face is easily formed, in contrast to the method offorming the TaCx electrode for pMIS 32. In the present embodiment, aTaCx film with C/Ta=1.0 is deposited at 100 nm by the simultaneoussputtering of the two targets including Ta and C. Techniques such as theCVD method or MBE method may be used for the deposition of this film.

Furthermore, if the surface of the TaCx electrode for nMIS 33 is treatedafter this step so that it is oxidized at a significantly smallthickness, the process resistance of the TaCx electrode in subsequentsteps is improved. Here, spike annealing at 1000° C. is carried outunder 1% oxygen atmosphere to form an oxide layer having a thickness of1 nm or less on the TaCx surface.

Next, as shown in FIG. 7D, the SiN film 36 is removed to remove the TaCxelectrode for nMIS 33 on the top of the n-type well area 22 by lift off.Specifically, SiN can be dissolved by, for example, a hot phosphoricacid process. In this case, since TaCx does not dissolve into a hotphosphoric acid solution regardless of its orientation, the structure inFIG. 7D can be obtained.

Next, as shown in FIG. 7E, a gate electrode resist pattern 37 is formedusing a conventional lithographic technique and etching technique, andthe TaCx electrodes 32 and 33 and the gate dielectric film 31 areprocessed by use of an ordinary etching gas such as a chlorine-based orbromine-based etching gas. In this process, the TaCx electrode for pMIS32 and the TaCx electrode for nMIS 33 are different in orientation butthe same in composition, and their etching rates are much the same, sothat the collective processing of the two transistors is possible.

Next, as shown in FIG. 7F, the resist pattern 37 is removed by an O₂asher treatment. At this point, the side surfaces of the TaCx electrodefor pMIS 32 and the TaCx electrode for nMIS 33 are slightly oxidized.Subsequently, the resist, residuals and the like which have not beencompletely removed by the O₂ asher are chemically removed by a mixtureof sulfuric acid and a hydrogen peroxide solution. At this point, theTaCx electrode for pMIS 32 and the TaCx electrode for nMIS 33essentially have strong chemical resistance, but in addition to this,have their surfaces (both upper surfaces and side surfaces) covered withthin oxides, so that they are not easily eroded by the mixture ofsulfuric acid and the hydrogen peroxide solution.

Next, as shown in FIG. 7G, the top of the n-type well area 22 isprotected by a resist (not shown), and n-type impurities such asphosphorus, arsenic and antimony are ion-implanted into the p-type wellarea 23. Further, the resist on the n-type well area 22 is removed, andthen the n-type extension layer 28 is formed by the spike annealing at1000° C. or more.

Next, as shown in FIG. 7H, the top of the p-type well area 23 isprotected by a resist (not shown), and p-type impurities such as boronand indium are ion-implanted into the n-type well area 22. The resist onthe p-type well area 23 is removed, and then the p-type extension layer26 is formed by the spike annealing at 1000° C. or more.

Next, as shown in FIG. 7I, the gate sidewall insulator 34 is formed in aconventional process. That is, an oxide film or the like is depositedover the entire surface on the substrate by the CVD method or the like,and then etched back by RIE or the like until the upper surfaces of theTaCx electrodes 32 and 33 are exposed.

Next, as shown in FIG. 7J, the top of the n-type well area 22 isprotected by a resist 38, and n-type impurities such as phosphorus,arsenic and antimony are ion-implanted into the p-type well area 23,thus forming an n-type implantation area 27 a.

Next, as shown in FIG. 7K, the resist 38 on the n-type well area 22 isremoved, and the top of the p-type well area 23 is protected by a resist39, and then p-type impurities such as boron and indium areion-implanted into the n-type well area 22, thus forming a p-typeimplantation area 25 a.

Next, as shown in FIG. 7L, the resist 39 on the p-type well area 23 isremoved, and a heat treatment at 900° C. or more is then carried out tocompletely activate the n-type diffusion layer 27 and the p-typediffusion layer 25. Subsequently, after the formation of the interlayerinsulator 35 and conventional steps such as planarization, theabove-mentioned structure shown in FIG. 1 can be obtained.

On the other hand, in the experiment using the XRD previously described,average information on the orientation of the TaCx film is only known,so that when a distribution of the orientation is present in the filmthickness direction, there is a possibility that the average orientationof the film is different from the orientation in the vicinity of thegate dielectric film. Since the work function of the MIS structure isdecided by the TaCx orientation in the vicinity of the interface of thegate dielectric film, it is necessary to check this distribution in thedepth direction.

FIGS. 10A and 10B are TEM photographs showing the section of a structurecomposed of the TaCx electrode for nMIS 33 (with a large number of (200)orientation components), SiO₂ and Si-MIS at the completion of the devicein the present embodiment. FIG. 10A shows a normal bright-field TEMimage, and FIG. 10B concerns an experimental result of a dark-field TEMimage for checking the continuity of crystal grains within the TaCxelectrode. In the dark-field image, white parts indicate TaC crystalgrains oriented in a particular direction.

It has been found from the result of dark-field observation in FIG. 10Bthat continuous single TaC grains are formed in the film thicknessdirection. That is, in this embodiment, the proportion of the (200)orientation is higher in parts of the TaCx film having a thickness of100 nm contacting the gate dielectric film, and it has been confirmedthat this leads to a low work function.

As described above, according to the present embodiment, both the gateelectrode 32 of the p-channel MIS transistor 51 and the gate electrode33 of the n-channel MIS transistor 52 are formed of a Ta—C alloy, andthe crystal orientation ratios of TaC in the gate electrodes 32 and 33are optimally set, such that low threshold voltages of the respectivetransistors can be set, and it is possible to obtain a CMIS devicehaving the gate electrodes with low resistance and heat resistingproperties and without the problem of depletion. Moreover, the gateelectrodes of the respective MIS transistors are based on the samematerial, such that it is possible to prevent an increase in the numberof steps in the manufacture of this CMIS device, and no complicatedprocess is required.

SECOND EMBODIMENT

A schematic configuration of a semiconductor device according to asecond embodiment of the present invention is shown in FIG. 11, in whichthe same signs are assigned to the same parts as those in FIG. 1 andthese parts are not described in detail.

A CMIS device of the present embodiment has a structure in which a TaCxelectrode for nMIS 33 is disposed on the top of a TaCx electrode forpMIS 32 of a p-channel MIS transistor 51 in the structure of the firstembodiment. This structure has been devised to simplify the process offorming the TaCx electrode.

A method of manufacturing the semiconductor device of the presentembodiment will be described referring to FIGS. 12A to 12D. First, asshown in FIG. 12A, an n-type well area 22 and a p-type well area 23which are separated by an isolation insulator 24 are formed on an Sisubstrate 11. Subsequently, a gate dielectric material film 31 isdeposited over the entire surface on a wafer.

The high dielectric film that can be used includes, for example, anoxide or mixed oxide of rare-earth elements such as Ti, Hf, Zr and La,silicate or aluminate of rare-earth elements such as Ti, Hf, Zr and Laor a dielectric film in which nitrogen is added to the above materials,Si₃N₄, Al₂O₃, Ta₂O₅, TiO₂, La₂O₃, CeO₂, ZrO₂, HfO₂, SrTiO₃, Pr₂O₃ or adielectric film in which nitrogen is added to the above materials.

Here, HfSiON having a thickness of 3 nm (a ratio of 0.5 or less ofHf/Hf+Si, nitrogen concentration: 20-atomic percent) is deposited inaccordance with an MOCVD method by way of example. Methods of depositionthat can be used include an ALD method, an MBE method, a PVD method andthe like.

Subsequently, an SiN layer 36 is deposited on the gate dielectric film31 using a conventional process, and the SiN film 36 on the n-type wellarea 22 is only removed using a conventional lithographic technique andwet etching technique. Then, the TaCx electrode for pMIS 32 is depositedover the entire surface on the wafer, thus obtaining the structure inFIG. 12A. Here, the thickness of the TaCx electrode needs to be 1.5 nmor more. In the present embodiment, the thickness of the TaCx electrodeis 5 nm.

Next, as shown in FIG. 12B, the SiN layer 36 is removed by, for example,hot phosphoric acid etching to remove the TaCx electrode for pMIS 32formed thereon by lift off. In contrast to the first embodiment, thelift off method is used instead of dry etching for the removal of TaCx.This can avoid problems such as the introduction of damages into thegate dielectric film due to the dry etching, and a reduction in thethickness (over etching) of the gate dielectric film 31 on the top ofthe p-type well area 23 due to the fact that a limited selection ratiocan only be obtained.

Next, as shown in FIG. 12C, the TaCx electrode for nMIS 33 is depositedover the entire surface on the wafer. Then, as shown in FIG. 12D, aftera gate electrode resist pattern 37 is formed using a conventionallithographic technique and etching technique, the TaCx electrodes 32 and33 and the gate dielectric film 31 are processed by use of an ordinaryetching gas. In this process, the TaCx electrode for pMIS 32 and theTaCx electrode for nMIS 33 are different in orientation but the same incomposition, and their etching rates are almost the same, so that thecollective processing of the two transistors is possible.

Subsequently, after the removal of the resist and the formation of ann-type extension layer 28, a p-type extension layer 26, a gate sidewallinsulator 34, an n-type diffusion layer 27, a p-type diffusion layer 25and an interlayer insulator 35, the structure in FIG. 11 is completed.

With such a configuration, it is possible to obtain an advantage similarto that in the previous first embodiment, and it is also possible toreduce the damage of etching to the gate dielectric film 31 and to avoidthe thickness reduction of the gate dielectric film, such that a CMISdevice with higher performance can be achieved.

THIRD EMBODIMENT

A schematic configuration of a semiconductor device according to a thirdembodiment of the present invention is shown in FIG. 13, in which thesame signs are assigned to the same parts as those in FIG. 1 and theseparts are not described in detail.

A CMIS device of the present embodiment has a structure in which, in thestructure of the first embodiment, there are, on a TaCx electrode forpMIS 32 in a p-channel MIS transistor 51, a silicon gate buffer TaCxlayer 41 and a p⁺ silicon gate electrode 42 thereon, and there are, on aTaCx electrode for nMIS 33 in an n-channel MIS transistor 52, a silicongate buffer TaCx layer 41 and an n⁺ silicon gate electrode 43.

In this structure, a silicon gate is disposed on the uppermost portionof the gate electrode to enhance process compatibility. A method ofmanufacturing the semiconductor device of the present embodiment will bedescribed referring to FIGS. 14A to 14H.

First, as shown in FIG. 14A, an n-type well area 22 and a p-type wellarea 23 which are separated by an isolation insulator 24 are formed onan Si substrate 11. Subsequently, a gate dielectric material film 31,the TaCx electrode for pMIS 32 and an SiN layer 36 are consecutivelydeposited over the entire surface on a wafer. Then, the SiN layer 36 andthe TaCx electrode for pMIS 32 on the top of the p-type well area 23 areremoved by a conventional lithographic technique and etching technique,and a resist is then removed, thereby obtaining the structure in FIG.14A.

Here, while any gate dielectric film may be used in the presentembodiment, HfSiON having a thickness of 3 nm (Hf/Hf+Si≅0.5, nitrogenconcentration: 20 atomic percent) is deposited in accordance with anMOCVD method by way of example. Methods of deposition that can be usedinclude an ALD method, an MBE method, a PVD method and the like.Moreover, the TaCx electrode for pMIS 32 is formed at a thickness of 6nm, and the SiN layer 36 is deposited at a thickness of 50 nm. The TaCxelectrode for pMIS 32 needs to be larger than 5 nm for the reasondescribed later.

Next, as shown in FIG. 14B, the TaCx electrode for nMIS 33 is depositedover the entire surface on the wafer. Then, as shown in FIG. 14C, theSiN layer 36 is removed by a hot phosphoric acid treatment to remove theTaCx electrode for nMIS 33 covering the top of the SiN layer by liftoff.

Next, as shown in FIG. 14D, the silicon gate buffer TaCx layer 41 and anon-doped silicon 44 are consecutively deposited over the entire surfaceon the wafer. The composition ratio (C/Ta) of the silicon gate bufferTaCx layer 41 is limited to 1.5 or more due to requirements describedlater. Moreover, the thickness thereof needs to be 5 nm or more for thereason described later. The silicon gate buffer TaCx layer 41 in thepresent embodiment has a C/Ta equal to 2.7 and a thickness of 10 nm.Here, Ge may be added to the non-doped silicon layer in a ratio of about0.3 or less of Ge/Ge+Si, and the thickness thereof is 100 nm in thepresent embodiment.

Next, as shown in FIG. 14E, a gate electrode resist pattern 37 is formedusing a conventional lithographic technique and etching technique. Usingthis resist pattern 37 as a mask, the non-doped silicon 44, the silicongate buffer TaCx layer 41, the TaCx electrode for pMIS 32, the TaCxelectrode for nMIS 33 and the gate dielectric film 31 are collectivelyetched by an ordinarily used etching gas.

Next, as shown in FIG. 14F, the resist pattern 37 is removed by an O₂asher treatment. At this point, the side surfaces of the silicon gatebuffer TaCx layer 41, the TaCx electrode for pMIS 32 and the TaCxelectrode for nMIS 33 are slightly oxidized. Subsequently, the resist,residuals and the like which have not been completely removed by the O₂asher are chemically removed by a mixture of sulfuric acid and ahydrogen peroxide solution.

In contrast to the first and second embodiments, the top of the TaCxelectrode is covered with the non-doped silicon 44 and the end facethereof is only slightly exposed in the present embodiment. The slightlyexposed surface of the TaCx electrode is covered with a thin oxide.Thus, the gate stacked structure in the present embodiment is moredifficult to be eroded by the mixture of sulfuric acid and the hydrogenperoxide solution than the structures in the first and secondembodiments, and has a greater margin of process conditions. Forexample, the structural resistance properties of the present embodimentare effective when a long-time treatment is carried out to morethoroughly remove the residuals.

Next, as shown in FIG. 14G, an n-type extension layer 28 and a p-typeextension layer 26 are formed in a process similar to those in the firstand second embodiments. Further, in a process step similar to those inthe first and second embodiments, a gate sidewall insulator 34 isformed, and an n-type diffusion layer 27 and a p-type diffusion layer 25are then formed, as shown in FIG. 14H. Subsequently, after the formationof an interlayer insulator 35 and conventional process steps such asplanarization, the structure shown in FIG. 13 can be obtained. Thesilicon gate electrodes 42 and 43 may be silicided to reduce theresistance thereof.

According to the present embodiment, device characteristics similar tothose in the first embodiment can be achieved with a significantly highprocess resistance by covering the TaCx layer with the silicon gate. Itis to be noted that the buffering layer for the silicon gate is formedby totally the same constituting elements as those of the metal gate forcontrolling the work function such that an extremely highly stable gatestacked structure can be provided.

In prior arts, when a silicon gate is stacked on the top of the metalgate for controlling the work function, impurities for reducing theresistance of silicon diffuse into the metal gate, which causesdisadvantages such as the modulation of the work function of the metalgate and a decrease in the impurity concentration of the silicon gate.On the contrary, such disadvantages are avoided if a metal gate havingan amorphous structure such as TaSiN is used for the buffering layer forsilicon.

However, there has heretofore been no material other than TaSiN as anamorphous metal material suitable for the buffer layer for the silicongate which prevents the intrusion of impurities. On the other hand, thedual metal gate for controlling the work function is made of a materialother than TaSiN. Mutual diffusion is easily caused by a thermaltreatment in such a stacked structure having elements of differentkinds. Thus, elements such as Ta, Si and N diffuse to the inside of thedual metal gate for controlling the work function, so that there hasbeen a high possibility that the work function results in an unintendedvalue.

In the present embodiment, a TaCx layer whose orientation is changed isused as the metal gate for controlling the work function, and a TaCxlayer in which C/Ta is increased to 1.5 or more so that its structurebecomes amorphous is used as the buffer layer for the silicon gate.Since the work function controlling metal gate and the buffer layer aremade of the same elements, the disadvantages caused due to the use ofthe conventional elements of different kinds such as TaSiN arecompletely removed.

C/Ta of the TaCx electrode for pMIS 32 and the TaCx electrode for nMIS33 in the present embodiment has to be 0.5 or more and 1.5 or less fromFIGS. 4 to 6 as the limitation for these electrodes to be crystallized.

Furthermore, the thickness of the TaCx electrode for pMIS 32 and theTaCx electrode for nMIS 33 for controlling the work function in thepresent embodiment needs to be larger than 5 nm. The reason is that ifthe thickness is equal to or smaller than this, the work function of thesilicon gate buffer TaCx layer 41 is active, so that a threshold voltagecannot be controlled by the work functions of the lower layer electrodes32 and 33.

Furthermore, regarding the composition of the silicon gate buffer TaCxlayer 41 in the present embodiment, this layer is amorphous or has astructure in which it is phase-separated into a matrix and precipitatessized at 5 nm or less, so that C/Ta needs to be 1.5 or more (see FIGS. 4and 6). This makes it possible to efficiently suppress the diffusion ofimpurities from the silicon gate.

FIG. 15 is a sectional TEM image of a TaCx film in the case of(C/Ta)≅2.7. The TaCx film shows black and white contrast. Ta accumulatesin black places, and white places are rich in carbon. The sizes of areaswhere Ta accumulates are 1 nm or less in this composition.

FIG. 16 is a schematic diagram showing the characteristics of the TaCxgate electrode in the present embodiment. TaC precipitates having adiameter of 5 nm or less are formed in a C-rich TaCx (2<x) matrix. TheTac precipitates may be crystallized or in an amorphous state. The TaCx(2<x) matrix is in an amorphous state. The Tac precipitates are shown inblack in the above-mentioned experiment results in FIG. 15.

Furthermore, the thickness of the silicon gate buffer TaCx layer 41needs to be 5 nm or more. The reason is that the above-mentioned effectof suppressing the intrusion of impurities is not achieved if the TaCxelectrode layer is smaller than this thickness.

FOURTH EMBODIMENT

A schematic configuration of a semiconductor device according to afourth embodiment of the present invention is shown in FIG. 17, in whichthe same signs are assigned to the same parts as those in FIG. 1 andthese parts are not described in detail.

A CMIS device of the present embodiment has a structure having: a gatestacked structure wherein a first element precipitated layer 46 isdisposed on the top of a gate dielectric film 31 of a p-channel MIStransistor 51, on which a TaCx electrode for pMIS 32 and a metalsilicide 45 are further stacked in this order; and a gate-stackedstructure wherein a second element precipitated layer 47 is disposed onthe top of a gate dielectric film 31 in an n-channel MIS transistor 52,on which a TaCx electrode for nMIS 33 and a metal silicide 45 arefurther stacked in this order.

In the structure of the present embodiment, the element precipitatedlayer is disposed at an interface with the gate dielectric film of theTaCx electrode for p(n)MIS of the p(n)-channel MIS transistor, such thatthe work function can be higher for pMIS and lower for nMIS than thosedescribed in the first to third embodiments, thereby making it possibleto provide a high-performance CMIS device with a lower thresholdvoltage.

A method of manufacturing the semiconductor device of the presentembodiment will be described referring to FIGS. 18A to 18I. First,process steps similar to those in the third embodiment are carried outto obtain the structure in FIG. 18A similar to that in FIG. 14C. Here,the TaCx electrode for pMIS 32 is formed on an n-type well area 22, andthe TaCx electrode for nMIS 33 is formed on a p-type well area 23.

Next, a non-doped silicon 44 and an SiN film 36 are deposited in thisorder over the entire surface on a wafer in FIG. 18A, thus obtaining thestructure in FIG. 18B. Both the non-doped silicon 44 and the SiN film 36can be formed by an ordinarily used deposition technique such as CVD.Moreover, germanium up to about 30 atomic percent may be contained inthe non-doped silicon 44.

Next, a gate electrode pattern is formed by a resist in accordance witha photolithographic technique used in conventional LIS process steps,and the SiN film 36 is processed into the shape of a gate electrode.Subsequently, using the SiN film 36 as a mask, the non-doped silicon 44,the TaCx electrode for pMIS 32, the TaCx electrode for nMIS 33 and thegate dielectric film 31 are collectively processed, thus obtaining thestructure in FIG. 18C. This process can be carried out by a reactive ionetching using an etching gas containing chlorine.

Subsequently, an extension, gate sidewalls and a diffusion layer areformed as in the previous embodiment, and an interlayer insulator isdeposited and planarized, thus obtaining the structure in FIG. 18D.Here, in the process of forming the extension and the diffusion layer,impurities are not introduced to the non-doped silicon 44 because itstop is covered with SiN.

Next, as shown in FIG. 18E, a metal layer 48, here, Ni by way of exampleis deposited at 100 nm over the entire surface of the structure in FIG.18D.

Then, the wafer is thermally treated at a relatively low temperature sothat the metal layer 48 reacts with the non-doped silicon 44 in solidphase, and all the non-doped silicon is changed into the metal silicide45. This thermal treatment can be carried out under conditions includinga temperature ranging from 350 to 600° C., a time of about 60 seconds,and a nitrogen atmosphere. The time of the thermal treatment can besuitably changed, and an inert gas such as argon or hydrogen may be usedin the thermal treatment atmosphere. Under such experimental conditions,the NiSi (monosilicide) layer 45 is formed when Ni is used. Theunreacted Ni layer 44 remains on the top of the NiSi layer 45, and thiscan be immersed in a mixed solution of sulfuric acid and a hydrogenperoxide solution so that the Ni layer 44 alone is dissolved and theNiSi layer 45 remains on the wafer. Thus, the structure in FIG. 18F canbe obtained.

When Ge is contained in the non-doped silicon, metal germano-silicide,NiSiGe in the present embodiment, is formed by totally the same processsteps as the process described above. Unreacted Ni can be selectivelyetched in the same manner as NiSi.

Next, as shown in FIG. 18G, the top of the p-channel MIS transistor areais covered with a mask member 61 so that the n-channel MIS transistorarea is opened, and impurities are ion-implanted into the NiSi layer 45of the n-channel MIS transistor area 52. In this case, the kinds ofimpurities used are phosphorus, arsenic and antimony, an implantationamount is about 10¹⁵ to 10¹⁶/cm², and acceleration energy is conditionedin accordance with the mass of the impurities so that the impuritiesremain within the NiSi layer 45.

Furthermore, the structure in FIG. 18G is thermally treated toprecipitate the implanted impurities such as phosphorus to an interfacebetween the gate dielectric film 31 and the TaCx electrode for nMIS 33,and the second element precipitated layer 47 is formed, thus obtainingthe structure in FIG. 18H. The thermal treatment can be carried outunder conditions including a temperature between 400° C. and 600° C., atime of about 60 seconds, and an inert atmosphere containing nitrogen orthe like.

Next, as shown in FIG. 18I, the top of the n-channel MIS transistor areais covered with a mask member 62, and impurities are ion-implanted intothe NiSi layer 45 of the p-channel MIS transistor area. In this case,the kinds of impurities used are, for example, boron (B), BF₂ andaluminum (Al), an implantation amount is about 10¹⁵ to 10¹⁶ cm⁻², andacceleration energy is conditioned in accordance with the mass of theimpurities so that the impurities remain within the NiSi layer 45.

Subsequently, a thermal treatment is carried out, and the implantedimpurities such as boron is precipitated to an interface area betweenthe gate dielectric film 31 and the TaCx electrode for pMIS 32, and thenthe first element precipitated layer 46 is formed. The thermal treatmentcan be carried out under conditions including a temperature between 400°C. and 600° C., a time of about 60 seconds, and an inert atmosphere withnitrogen or the like. Then, the mask member 62 is removed, such that thestructure in FIG. 17 is achieved. The thickness of the first elementprecipitated layer 46 corresponds to one or more atomic layers and fiveor less atomic layers. One atomic layer makes it possible to obtain achange of the work function sufficiently stable for controlling thethreshold voltage, but with a thickness smaller than this, it isdifficult to obtain a work function change due to the modulation of theimpurities as shown in FIG. 19. With a thickness corresponding to fiveor more atomic layers, the work function possessed by the precipitatedimpurities starts to be active. In this case, a work function is shownwhich is totally different from the work function owing to the TaCxorientation and the modulation by the impurity precipitation that areadded together as shown in FIG. 19, so that the advantage of the presentinvention can not be obtained.

It is more desirable that the thickness of the impurity precipitatedlayer correspond to one or more atomic layers and three or less atomiclayers. In principle, the advantage of the present invention can beobtained if the impurity precipitated layer has one atomic layer, but areliable advantage can be expected when a somewhat thick impurityprecipitated layer is formed to allow for a margin of error,considering, for example, the possibility that the impurities diffuse toplaces other than the interface and the possibility that the impurityprecipitated layer is spatially nonuniformly formed. The advantage ofthe present invention can be obtained up to five atomic layers, but thelimit of thickness is optimally about three atomic layers.

This is concerned with the fact that the impurities are added by the ionimplantation after the formation of the electrode in the presentinvention. Typically, three atomic layers can be achieved by 1×10¹⁶/cm²,but 2×10¹⁶/cm² is required to create four atomic layers. Ions implantedto create four atomic layers are functionally wasteful. On the otherhand, ion implantation with a high current and a long time is requiredfor the ion implantation on the level of 10¹⁶/cm², and on this order, itis required in terms of cost to reduce the implantation amount as muchas possible. As described above, the limitation of three or less atomiclayers is decided by problems of manufacturing cost.

Here, the process has been described in which the first elementprecipitated layer 46 and the second element precipitated layer 47 areformed in separate thermal treatments. However, it is also possible toform both the element precipitated layers in the same thermal treatment.This is possible when impurity elements having about the same diffusioncoefficient in the metal silicide/TaCx stacked gate electrode are used.For example, this process can be achieved when a combination of impurityelements such as phosphorus for the n-channel MIS transistor and boronfor the p-channel MIS transistor is used. This simplifies themanufacturing process.

The present embodiment employs slightly complicated processing steps:after the metal silicide/TaCx electrode stacked gate electrode isformed, elements are implanted into the metal silicide, which arethermally diffusion and precipitated to the interface between the gatedielectric film and the TaCx electrode. In the present embodiment, boththe metal silicide and TaCx have polycrystalline structures, and theircrystal grain boundaries function as high-speed diffusion channels forthe impurity diffusion. Therefore, the impurity elements introduced intothe metal silicide relatively easily diffuse within the electrode, andare precipitated to the interface with the gate dielectric film. Sincethe diffusion within the metal gate occurs at a high speed at a lowtemperature of 600° C. or less, there is no fear that the impuritiesinfiltrate into the gate dielectric film 31 due to this diffusionprocess to deteriorate device characteristics.

FIG. 19 is a diagram for explaining the advantage of the presentembodiment. In the first to third embodiments, nearly ideal workfunctions are achieved by controlling the orientation of the TaCxelectrode, but a work function of about 4 eV is required for then-channel MIS transistor 52 and a work function of about 5 eV isrequired for the p-channel MIS transistor 51 in order to furtherdecrease the threshold voltage of the transistor. In the presentembodiment, the control of the work function achieved by the control ofthe orientation of TaCx is combined with the effects of modulation ofthe work function due to the element precipitation, thereby making itpossible to achieve the ideal work functions. Thus, it is possible toachieve a CMIS device with an almost ideal low threshold voltage.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details and representative embodiments shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit or scope of the general inventiveconcept as defined by the appended claims and their equivalents.

1-15. (canceled)
 16. A semiconductor device comprising: a substrate; anda p-channel MIS transistor formed on the substrate, having a gatedielectric film formed on the substrate, and a gate electrode formed onthe gate dielectric film, the gate electrode formed of a Ta—C alloy inwhich a crystal orientation ratio of a TaC (111) face in a filmthickness direction of the gate electrode [TaC (111) face/{TaC (111)face+TaC (200) face}] is 80% or more.
 17. The device according to claim16, wherein a composition ratio (C/Ta) of the gate electrode is 0.5 ormore and 1.5 or less.
 18. A semiconductor device comprising: asubstrate; and a p-channel MIS transistor formed on an n-typesemiconductor area, the p-channel MIS transistor having a gatedielectric film formed on the n-type semiconductor area, and a gateelectrode formed on the gate dielectric film, the gate electrodeincluding a lower layer gate electrode formed of a Ta—C alloy in which acrystal orientation ratio of a TaC (111) face in a film thicknessdirection of the lower layer gate electrode [TaC (111) face/{TaC (111)face+TaC (200) face}] is 80% or more, a middle layer gate electrodeformed on the lower layer gate electrode and formed of a Ta—C alloy inwhich the composition ratio (C/Ta) is 1.5 or more, and a upper layergate electrode formed on the middle layer gate electrode and formed ofp⁺-type silicon or p⁺-type silicon germanium.
 19. The device accordingto claim 18, wherein a composition ratio (C/Ta) of the lower layer gateelectrode is 0.5 or more and 1.5 or less.
 20. The device according toclaim 18, wherein a thickness of the lower layer gate electrode islarger than 5 nm.
 21. The device according to claim 18, wherein themiddle layer gate electrode is phase-separated into amorphous matricesand TaC precipitates.
 22. The device according to claim 18, wherein themiddle layer gate electrode is amorphous.
 23. A semiconductor devicecomprising: a substrate; and a p-channel MIS transistor formed on an-type semiconductor area on the substrate, including a gate dielectricfilm formed on the n-type semiconductor area, a lower layer gateelectrode formed on the gate dielectric film and formed of a Ta—C alloyin which a crystal orientation ratio of a TaC (111) face in a filmthickness direction of the lower layer gate electrode [TaC (111)face/{TaC (111) face+TaC (200) face}] is 80% or more, an upper layergate electrode formed on the lower layer gate electrode and made of ametal silicide, and an element precipitated layer formed in an interfacearea between the lower layer gate electrode and the gate dielectricfilm, the element being selected from the group consisting of boron andaluminum.
 24. The device according to claim 23, wherein the metalsilicide contains at least one selected from the group consisting of Ni,Co, Pt and Ir.
 25. The device according to claim 24, wherein the metalsilicide further contains germanium.
 26. The device according to claim23, wherein the element precipitated layer has three atomic layers orless.